The increasing demand for integrated circuits along with strict price/ performance goals, time constraints in design and deployment and the rapid developments in semiconductor process technology are driving us towards designs of 0.35 micron and below. These processes are known as deep sub micron or very deep sub micron technology. With the advent of deep sub micron technologies, conventional design flows and methodologies need to be appropriately enhanced. Thus, the current CAD environment supporting automated higher abstraction levels like system level synthesis as well as more manual and lower abstraction levels such as lay outing have to be correspondingly upgraded.